1. Field of the Invention
The invention relates to the field of circuit design and, more particularly, to floorplanning techniques for programmable logic devices.
2. Description of the Related Art
Programmable logic devices (PLD's) have become increasingly complex and heterogeneous. Modern PLD's, such as field programmable gate arrays (FPGA's), can include a variety of different components including, but not limited to, block random access memory (RAM), multipliers, processors, and the like. This increasing complexity makes circuit design more cumbersome.
Frequently, a PLD undergoes an iterative design process intended to improve the quality of the PLD design and to meet specific design criteria. Oftentimes, the changes to the design from one iteration to the next are incremental in nature. That is, modifications to the PLD design tend to be minor improvements as the design process nears completion and the performance of the PLD design approaches the design criteria.
Presently, when making a minor or incremental improvement to a PLD design, there is little or no guarantee that such an action will produce a predictable result. With reference to FPGA designs, for example, a designer is not assured that a minor change to the mapped netlist will produce a predictable placement and routing.
What is needed is a method, system, and apparatus, for attaining predictable results when implementing incremental changes to a PLD design.